The present invention relates to the so-called RAM (Random Access Memory) which has a large number of memory cells for storing charge carriers in a semiconductor as information sources and which has means for reading out the information stored in the cells and writing the information into the cells in accordance with appointed address signals, and more particularly to a very high density RAM which includes voltage amplifiers of very high sensitivity.
The prior-art structure of the so-called one-transistor type dynamic RAM (1 Tr-dRAM), which has been well known as a RAM employing charge carriers in a semiconductor as information sources and which uses one transistor and one capacitor as the constitutents of a memory cell, is shown in FIG. 1.
Referring to FIG. 1, numeral 1 designates a capacitor which stores signal charge carriers to serve as an information source, numeral 2 a MOS transistor (MOST) which functions as a word gate transistor, numeral 3 a word line which turns "on" or "off" the switch 2 in accordance with addressing in an X direction, and numerals 4 and 5 data lines which transmit the charge carriers. Numeral 6 collectively indicates an address decoder for the addressing in the X direction, and a word driver for driving the word lines 3 (hereinbelow, simply termed "X decoder"). Numeral 7 indicates an address decoder in a Y direction for selecting the data lines, and an input/output circuit (hereinbelow, simply termed "Y decoder" and "I/O circuit" respectively). Numeral 8 denotes a sense amplifier, numeral 9 (within a broken line) a dummy capacitor for producing a reference signal, and numeral 10 a dummy word gate MOST. The fact that one terminal of the capacitor 1 or 9 in the figure is indicated by a circle, signifies that it is connected to the highest D.C. voltage V.sub.cc of the system by way of example.
In such prior-art dRAM, when concrete examples of numerical values are mentioned, the charge carriers stored in the capacitor 1 of approximately 50 fF (f: femto-, 10.sup.-15) are shifted onto the data line 4 of approximately 2 pF, and the resulting voltage variation is detected. Accordingly, even a signal voltage v.sub.s having been near the highest voltage of the system (for example, 4 V) when stored in the capacitor 1 of the memory cell becomes as small as about 100 mV when detected, in the above exemplified case. For this reason, a highly accurate amplifier is needed with a simple detection method. As illustrated in FIG. 1, therefore, the charge carriers stored in the dummy capacitor 9 (within the broken line) having a capacitance equal to 1/2 of that of the capacitor 1 by way of example (25 fF in the exemplified case) are taken out on the data line 5, and the information stored in the capacitor 1 is decided by the differential sense amplifier 8.
However, with this approach, a highly accurate sense amplifier is required for each pair of data lines, and the necessary complicated circuitry for this which exhibits a high performance and which needs electric power cannot be employed for a very high density RAM. Even with the method as stated above, therefore, the signal voltage on the data line is limited to approximately 100 mV with a margin in practical use included. Accordingly, the ratio C.sub.S /C.sub.D between the storage capacitance C.sub.S of the memory cell and the capacitance C.sub.D of the data line needs to be set at or above approximately 1/40, and it is difficult to make the storage capacitance C.sub.S much smaller than the above example. This has formed a serious hindrance to enhancement in the packing density of the dRAM.
As a solution to the above problem, a method employing a charge-transfer sense amplifier has been proposed (L. G. Heller et al, Digest of Technical Papers for ISSCC, pp. 112-113, February 1975; ISSCC being short for "International Solid State Circuit Conference").
FIG. 2 is a diagram for explaining this principle. In the figure, parts 1-8 are similar to those in FIG. 1. The point of difference from FIG. 1 is that a MOST 11 is inserted between the sense amplifier 8 and the data line 4.
A voltage V.sub.R is applied to the gate electrode 12 of the MOST 11 so as to set the potential of the data line 4 at V.sub.R -V.sub.T11 (where V.sub.T11 denotes the threshold voltage of the MOST 11). When the charge carriers have been read out from the capacitor 1 of the memory cell, the potential of the data line changes by .DELTA.V.sub.D (100 mV in the foregoing example), and the MOST 11 falls into the "on" state to the extent of .DELTA.V.sub.D (that is, V.sub.GS11 -V.sub.T11 =.DELTA.V.sub.D where V.sub.GS11 denotes the voltage between the gate and source of the MOST 11). When the voltage of the input part 13 of the sense amplifier 8 is set to be sufficiently high (in actuality, a reset transistor is provided), the data line is charged until its potential returns to V.sub.R -V.sub.T11 (V.sub.GS11 -V.sub.T11 =0 V). .DELTA.V.sub.D .perspectiveto.(C.sub.S /C.sub.D)v.sub.S and .DELTA. V.sub.I .perspectiveto.(C.sub.D /C.sub.I).DELTA.V.sub.D hold (when v.sub.S denotes the signal voltage having been stored in the capacitor 1 and Q.sub.S the quantity of signal charges, Q.sub.S =C.sub.S .multidot.V.sub.S holds, and in the above, .DELTA.V.sub.I : the voltage variation of the input part of the sense amplifier, and C.sub.I : the capacitance of the input part). Therefore, .DELTA.V.sub.I .perspectiveto.(C.sub.S /C.sub.I)v.sub.S holds. Since the value C.sub.I is readily made approximately equal to the capacitance C.sub.S of the memory cell, a voltage on the order of 1 V is claimed to appear at the input part of the sense amplifier. It has been actually impossible, however, to put this measure into practical use. The reason is that, when the gate-source voltage V.sub.GS11 of the MOST 11 is near the threshold voltage thereof, the MOST 11 is in the mode of operation of tailing current, the value of which is very small, so an almost infinite time is required for the charging of the capacitance C.sub.D as compared with the operating speed of the RAM (refer to "Nikkei Electronics", dated Feb. 19, 1979, pp. 152-153).
In order to overcome the disadvantage of the charge-transfer sense amplifier as described above, methods which derive a signal from a vertical signal output line by the use of bias charges have been proposed in solid-state imaging devices (Japanese Laid-open Patent Application No. 51-107025, Japanese Laid-open Patent Application No. 55-44788). Since, however, they concern the imaging devices, they are essentially different from the case of the RAM in such points that the writing function need not be considered and that conversely circuitry for anti-blooming and/or anti-smearing is required. Moreover, the above proposals have the serious drawbacks of the structure (Japanese Laid-open Patent Application No. 51-107025) and the driving method (Japanese Laid-open Patent Application No. 55-44788) in which the signal charges are read out in a non-saturation mode thereby to sense current. Therefore, their effects in practical use are very low as will be stated later.
Further, a solid-state imaging device in which a charge transfer device is disposed as a horizontal read-out circuit has been proposed (Japanese Laid-open Utility Model Registration Application No. 54-5100). Although this system is excellent for the solid-state imaging device, signals are read out serially due to the use of the charge transfer device, and the dynamic RAM which needs to refresh signals becomes very complicated in structure and is difficult for use.